1. Field of the Invention
The present invention relates to a memory read control circuit, and in particular, to a read control circuit for reading data from DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory).
2. Description of the Related Art
With rapid progress of an IT (Information Technology) technique, a transmission rate of data communicated on a transmission line has increasingly become in high speed. For the reason, an electrical circuit mounted in an apparatus connected to a transmission line is required to have a function of performing high speed processing in a large scale, and circuitry using DDR SDRAM is performed frequently.
In order to notify a receiver of timing of transferring data, DDR SDRAM uses a data strobe signal (DQS). The DQS is a bidirectional strobe signal and functions as an operation reference clock of a data input/output at the time of a read/write operation. In read operation, since an edge of the DQS and an edge of read data coincide, when read data is received from the DDR SDRAM, the received DQS is delayed inside to a center of the read data.
When a read command (READ) is received when the DDR SDRAM is in an active state, the DQS changes from a high impedance (Hi-Z) state to a low level. This low level period is a preamble. The preamble is generated about 1 clock before a first data is outputted. With following the preamble, the DQS is toggled at the same frequency as a clock signal in a period equivalent to a burst length when valid data is on a data input/output terminal (DQ). The low level period after last data is transferred is a postamble. The postamble is generated for about ½ clocks from an edge of the last data.
The DQS transits from the high impedance state to a preamble, and shifts to a high impedance state from the postamble. When an intermediate level in this high impedance state becomes a signal of an undefined level and spreads inside a memory interface, there is a possibility that read data in a data incorporation unit may be destroyed before read data is latched by a data synchronizer. Then, in order to avoid such data becoming unfixed, a DQS mask circuit for keeping an undefined level from spreading to an input side of the DQS is mounted in a circuit in a memory read side (e.g., patent documents 1 and 2: Japanese Patent Laid-Open Nos. 2005-276396 and 2006-260322).
A memory interface control circuit equipped with such a DQS mask circuit can improve glitch noise resistance of read-out data and can relax restrictions of physical arrangement relationship between memory and a memory controller LSI, at the time of transfer of read-out data between the memory and memory controller LSI.
In the present invention, the following analyses are performed.
Patent documents 1 and 2 disclose interface control circuits which are excellent in glitch noise resistance regarding a data strobe signal to data which is burst transferred with corresponding to a read command. Specifically, examples in cases that a burst transfer with a read command is 4 or 8 are mentioned. However, when it is going to give further flexibility, for example, when a burst transfer is 1 and this is made to be applied to continuous read commands, it becomes necessary to perform a redesign of a circuit with corresponding to a transfer mode. That is, a customized design according to each product is required, and hence, flexibility is lost.